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Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs - This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. - The J and K data is processed by the flip-flop on the falling edge of - The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times - A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. (Ics chips:DM74LS112AN dual edge-triggered j-k flip-flop was posted and is owned by: Melisa Gregory) |
Melisa_Gregory@chicagopartsnetwork.com (Melisa Gregory) for more information.
