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- When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the (Ics chips:DM74LS125AN quad 3-state non-inverting buffer was posted and is owned by: Ellen Perez) |
e_perez@chicagopartsnetwork.com (Ellen Perez) for more information.
